A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of a flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (SixOy). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
A typical configuration of an array of flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to drains. The sources of the flash memory cells are commonly coupled together.
The flash memory cell stores data by holding charge within the floating gate. In a write or program operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
A common failure in flash memory is a programming failure due to an over-erased cell. During an erase process, not all bits in an array erase in the same way. Typically, threshold voltages for an array of flash memory that have been erased fall within a Gaussian distribution. A reference voltage, and its corresponding current, provide a means to determine whether a memory cell has been erased. Threshold voltages of memory cells below the reference voltage indicate that those memory cells are erased.
When a column of flash memory cells, in an array of flash memory cells, is erased in parallel, some memory cells are erased very quickly (fast bits) while other memory cells are harder to erase (slow bits). A small percentage of over-erased bits having threshold voltages below 0 volts can occur. The fast bits create a non-Gaussian distribution of threshold voltages, which leads to a wider distribution of threshold voltages.
Unfortunately, having an over-erased cell on the same column line with a selected memory cell, or bit, can cause a failure when the selected memory cell is read during a verify operation, such as a erase verify operation. The over-erased cell produces a leakage current and causes the entire column to malfunction. As a result, the state of the selected memory cell may be falsely reported. For example, in an erase verify operation, the selected memory cell may be falsely verified to be erased, when in fact, the selected memory cell is still programmed. Specifically, in an erase verify operation, when determining that the selected memory cell is still programmed, the current that is read from the column should be below the reference current (IRef) that corresponds to the reference threshold voltage. This corresponds to an improperly erased cell having a higher threshold voltage and producing a current below IRef, where IRef is the erased cell reference current used for comparison.
However, if an over-erased cell is in the same column as that of the selected memory cell that is still programmed even after an array wide erase operation, the over-erased cell has a threshold voltage that is less than 0 and produces a leakage current (ILeak). As such, the total current read from the column will include the current from the selected memory cell (IProgram) and the leakage current. If the sum of IProgram+ILeakage>IRef, then the total current being read from the column is greater than the reference current, and the programmed cell appears to be erased, when in fact it is still improperly programmed.
What is needed is a method for detecting the proper states of flash memory cells.